The present invention relates to a semiconductor storage apparatus having a plurality of memory-cells arranged, forming array which is composed of regular memory-cell blocks and redundant memory-cell blocks.
More particularly, the invention relates to a semiconductor storage apparatus in which the regular memory-cell blocks are grouped into new regular memory-cell blocks in accordance with the column address of any defective regular memory-cell that has been found.
The grouping of the redundant memory-cell blocks are changed in accordance with the grouped regular memory-cell blocks.
The grouped redundant memory-cell blocks replace the corresponding regular memory-cell blocks including the defective cell and to a manufacturing method therefor.
FIG. 1 is a schematic structural diagram showing an example of a conventional semiconductor storage apparatus.
Referring to FIG. 1, reference numeral 11 represents a row decoder, 12 represents one of 16 memory-cells each of which is composed of 64 columns, 13 represents one of four defect relieving redundant memory-cells each of which is composed of four columns, 14 represents one of two second data lines (2DQ) formed in a sense amplifier region, 15 represents a read amplifier and 16 represents the sense amplifier region. I/O terminals 0 to 3 are connected to the read amplifier 15.
FIG. 2 is a circuit diagram showing a portion of the semiconductor storage apparatus shown in FIG. 1.
The second data line (2DQ) 14 is, in each pair (DQ), connected to a sense amplifier 18 through a FET 17. The sense amplifier 18 is connected to a memory-cell section 20 through a first data line 19. The memory-cell section 20 is connected to a word line 21. The gate of the FET 17 is connected to a column selection line 22. Reference numeral 23 represents a memory-cell array region.
A circuit which pre-changes the first data line is omitted.
FIG. 3 is a circuit diagram showing the memory-cell section 20 shown in FIG. 2.
The first data line 19 is connected to a memory-cell 25 of a capacitor storage device through a transfer gate, for example, a FET 24. The gate of the FET 24 is connected to the word line 21.
In the conventional memory shown in FIGS. 1 to 3 having the structure for reading data from the memory-cell 25 to the outside and formed such that the second data lines 14 are formed in the sense amplifier region 16 in parallel to the word line 21, the column selection line 22 is formed in parallel to the first data line 19 in the memory-cell array region 23. Thus, four bits of memory-cell data amplified by the sense amplifier 18 are output to the second data line 14 so that data is read to the outside.
However, when a large quantity of data is read from one memory-cell array, for example, when 128-bit data is read from the memory-cell array, the above-mentioned structure of the data lines, having the necessity of causing 128 pairs of the second data lines 14 to pass through the sense amplifier region 16, suffers from a problem in that the area of the sense amplifier region 16 is enlarged excessively.
FIG. 4 is a schematic diagram showing the structure of a conventional semiconductor storage apparatus arranged to be capable of solving the above-mentioned problem.
Referring to FIG. 4, reference numeral 31 represents a row decoder, 32 represents one of 16 memory-cells each of which is composed of 64 columns, 33 represents one of two defect relieving redundant memory-cells each of which is composed of 8 columns, 34 represents 16 data lines (8DQ) formed into 8 pairs to run parallel to the first data lines 39 shown in FIG. 5, 35 represents one of a group of four column selection lines formed into two pairs in the sense amplifier region 16 to run parallel to the word line and 36 represents redundant data line, in the memory-cell array region 23, formed into a pair to run parallel to the first data line 19.
FIG. 5 is a circuit diagram showing a portion of the semiconductor storage apparatus shown in FIG. 4. FIG. 6 is an enlarged circuit diagram showing the portion Z shown in FIG. 5.
The pairs of the second data lines (8DQ) 34 are connected to 8 sense amplifiers 38 through the corresponding FETs 37. Moreover, each of the sense amplifiers 38 is connected to the memory-cell section 40 through the first data line 39.
The memory-cell section 40 is connected to a word line 41, while the gates of FETs 37 are connected to 8 corresponding column selection lines 35. The memory-cell section 40 has a structure similar to that shown in FIG. 3.
In an overlaid-DQ structure semiconductor storage apparatus, as shown in FIGS. 4 and 5, having the second data lines 34 formed in parallel to the first data lines 39 on the memory-cell array thereof, 8 column selection lines 35 select memory-cells in one column unit from memory-cells in 8 column units to read data to one pair of the second data lines (DQ). Therefore, 8 pairs of the second data lines (8DQ) 34 are required to read memory-cells in 64 column units.
Therefore, memory-cells in 128 column units can simultaneously be selected by 16 sets of 8 pairs of the second data lines (8DQ) 34. As described above, memory-cells in 128 column units can simultaneously be selected by a structure in which 8 column selection lines 35 are formed in the sense amplifier region 16 and 16 sets of 8 pairs of the second data lines 34 are formed in the memory-cell array region 23. As a result, a large quantity of data can simultaneously be read without considerably enlargement of the areas of the memory-cell array region 23 and the sense amplifier region 16.
However, the above-mentioned structure encounters a problem in that the defect relieving efficiency in the column direction deteriorates. Providing that the defect relieving redundant memory-cell have 16 column units, the degree of freedom to relieve defects of the semiconductor storage apparatus shown in FIG. 1 and that shown in FIG. 4 are subjected to a comparison. The defect relieving redundant memory-cells of the semiconductor storage apparatus shown in FIG. 1 are able to relieve four sets of four column units (which are units for one column selection line), that is, four defects in the direction of column. However, the defect relieving redundant memory-cells of the semiconductor storage apparatus shown in FIG. 4 are able to relieve only two sets of 8 column units (which are units for one pair of the second data lines), that is, only two defects in the direction of column.
This means a fact that the defect relieving efficiency is made to be substantially halved. If four defects in the direction of column are required to be relieved, four sets of the defect relieving redundant memory-cells 33 in 8 column units must be provided. In this case, the number of the defect relieving redundant memory-cells are made to be two times. Thus, the area of the chip is enlarged by several percents.
Referring to FIG. 7, the same elements as those shown in FIG. 4 are given the same reference numerals and the structures of the same elements are omitted from description.
As described above, the overlaid-DQ structure semiconductor storage apparatus, which is capable of reading a large quantity of data without the necessity of enlarging the area of the chip, has the problem in that the defect relieving efficiency in the direction of column or the problem in that the area is enlarged if the same defect relieving efficiency is required to be realized.